1. Field of the Invention
The present invention relates to a fully differential sampling circuit for single end input that performs fully differential sampling/holding on a single end input signal without an inverter amplifier and converts the signal to a fully differential sampling signal, and concerns an oversampling delta sigma A/D converter using the same.
Further, the present invention is characterized in that a linear term of voltage dependence of a capacitance is complementarily canceled regarding a capacitor formed on a semiconductor integrated circuit to reduce a sampling error appearing when an input signal is sampled, that is, to reduce second harmonic distortion which has been normally caused by a linear term of voltage dependence of capacitance of the capacitor.
2. Description of the Related Art
Recently, when an analog signal is handled on a semiconductor integrated circuit, the following methods are available: a method for handling a continuous-time analog signal as it is by an operational amplifier, a resistor, and a capacitor, and a method for sampling an analog signal at a predetermined sampling rate and processing the signal in a sampling time system.
In the latter method, an input differential pair is composed of a MOS transistor, and a MOS operational amplifier having no input leakage current has been developed. Thus, a so-called switched capacitor circuit has appeared, which is composed of an operational amplifier, a MOS switch, and a capacitor. The switched capacitor has been mainstream of analog signal processing until recently.
In addition to a switched capacitor filter, such technology of the switched capacitor circuit is applicable to a so-called a delta sigma modulator, which combines integrators on multiple stages and an A/D converter of a small number of bits and sends feedback of the result of A/D conversion to a first stage. The switched capacitor circuit is also applied to an oversampling delta sigma A/D converter which has been recently mainstream regarding an audio band.
Such a switched capacitor circuit firstly came as a single end type having only a signal system of a signal path. However, in response to the needs for a single chip combined with a digital circuit, which has become faster by the recent fine process, and a noise solution, a so-called fully differential switched capacitor circuit has become mainstream, in which signal paths are divided into two positive and negative systems and a difference therebetween is used as a signal level to cancel high-speed digital noise as in-phase noise.
Meanwhile, an ordinary analog signal is a single end signal centered at a certain input reference potential. Thus, in order to capture a single end signal to the fully differential switched capacitor circuit, the signal needs to be converted to a fully differential signal. Namely, when an input single end signal is used as a positive signal, it is necessary to produce a negative signal by inverting the positive signal.
The most typical method for producing a negative signal is to make inversion by an inverter amplifier and supply both of positive and negative signals to a fully differential switched capacitor circuit while maintaining a continuous-time system. As shown in FIG. 6, a single end input signal is used as a positive signal, the single end input signal is supplied to a positive signal input terminal 3 of a fully differential switched capacitor circuit 2 on a subsequent stage, an inverted signal is produced by an inverter amplifier 7 constituted by a single end operational amplifier 4, an input resistor 5, and a feedback resistor 6, and the inverted signal is supplied to a negative signal input terminal 9 of the fully differential switched capacitor circuit 2.
The fully switched capacitor circuit 2 samples/holds a fully differential input signal, which is a difference between positive signal input and negative signal input, according to a switched capacitor operating clock (CK). The fully switched capacitor circuit 2 performs a predetermined switched capacitor operation, outputs positive and negative signals respectively from a positive signal output terminal 11 and a negative signal output terminal 12, and uses a difference between the output signals as a fully differential output signal.
As a specific example of the fully switched capacitor circuit, FIG. 7 shows a fully differential switched capacitor integrator having the function of sampling/holding. The following will focus on the sampling/holding function and increased accuracy of the function.
Further, as shown in FIG. 8(A), a capacitor 15 formed on a semiconductor substrate is generally constituted by two layers of polysilicon electrode plates 16 and 17 that contain N-type impurity such as phosphorus and a dielectric film 18 composed of an oxide film and the like between the electrode plates 16 and 17. The capacitor 15 is formed on a semiconductor substrate 19 such as a silicon substrate. As symbols shown in a circuit diagram, capacitor symbols are used to separately represent first polysilicon serving as a lower layer and second polysilicon serving as an upper layer. The capacitor symbols represent the former layer as a curve and the latter layer as a straight line (FIG. 8(B)).
The fully differential switched capacitor integrator of FIG. 7 is constituted by a fully differential operational amplifier 20, which has negative and positive input terminals 21 and 22 and positive and negative output terminals 23 and 24, a first integral capacitor 25 which is disposed between the negative input terminal and the positive output terminal of the fully differential operational amplifier 20 and has a capacitance Ci, a second integral capacitor 26 which is disposed between the positive input terminal and the negative output terminal and has a capacitance Ci, a first sampling capacitor 27 which is disposed between the input terminal 3 and the negative input terminal (so-called summing node on the positive side) 21 of the fully differential operational amplifier 20 to perform the sampling/holding function of a positive signal and has a capacitance Cs, four switches 31 to 34, a second sampling capacitor 28 which is disposed between the input terminal 9 and the positive input terminal (so-called summing node on the negative side) 22 of the fully differential operational amplifier to perform the sampling/holding function for a negative signal and has a capacitance Cs, and four switches 41 to 44.
The following will discuss the operation of the integrator configured thus.
When an operating clock CK is in positive phase (xcfx86=H, xcfx86B=L), the switches 31, 32, 41, and 42 are turned on, and the switches 33, 34, 43, and 44 are turned off. Therefore, a lower layer electrode of the first sampling capacitor 27 is connected to the input terminal 3 via the switch 31, and an upper layer electrode is connected to an operating common potential (analog ground) via the switch 32. Further, a lower layer electrode of the second sampling capacitor 28 is connected to the input terminal 9 via the switch 41, and an upper layer electrode is connected to the operating common potential via the switch 42.
As a result, a positive signal from the input terminal 3 and a negative signal from the input terminal 9 are sampled at the first and second sampling capacitors 27 and 28. When the input terminal 3 has a potential of VIN+ and the input terminal 9 has a potential of VINxe2x88x92, charges Q1 and Q2 of the following equations are respectively accumulated in lower layer electrodes 27a and 28a of the first and second sampling capacitors 27 and 28.
Q1=(VIN+)xc2x7Cs 
Q2=(VINxe2x88x92)xc2x7Cs 
Moreover, charges Q1xe2x80x2 and Q2xe2x80x2 of the following equations are respectively accumulated in upper layer electrodes 27b and 28b of the sampling capacitors 27 and 28.
Q1xe2x80x2=xe2x88x92Q1=xe2x88x92(VIN+)xc2x7Cs 
Q2xe2x80x2=xe2x88x92Q2=xe2x88x92(VINxe2x88x92)xc2x7Cs 
In contrast, when the operating clock CK is in opposite phase (xcfx86=L, xcfx86B=H), the switches 31, 32, 41, and 42 are turned off and the switches 33, 34, 43, and 44 are turned on. Thus, the lower layer electrode of the first sampling capacitor 27 is connected to the operating common potential via the switch 33, and the upper layer electrode is connected to the input terminal 21 via the switch 34. Further, the lower layer electrode of the second sampling capacitor 28 is connected to the operating common potential via the switch 43, and the upper layer electrode is connected to the input terminal 22 via the switch 44.
As a result, the charges Q1xe2x80x2 and Q2xe2x80x2 accumulated in the sampling capacitors 27 and 28 are released and shifted to the upper layer electrodes of the first and second integral capacitors 25 and 26.
Therefore, the following charges xe2x88x92Q1xe2x80x2 and xe2x88x92Q2xe2x80x2 are collected in the lower layer electrodes on the output terminals of the first and second integral capacitors 25 and 26.
xe2x88x92Q1xe2x80x2=(VIN+)xc2x7Cs 
xe2x88x92Q2xe2x80x2=(VINxe2x88x92)xc2x7Cs 
Thus, in the fully differential operational amplifier, the positive output terminal 11 has a potential VOUT+ and the negative output terminal 12 has a potential VOUTxe2x88x92 according to the following equations.
VOUT+=xe2x88x92Q1xe2x80x2/Ci=(VIN+)xc2x7Cs/Ci 
VOUTxe2x88x92=xe2x88x92Q2xe2x80x2/Ci=(VINxe2x88x92)xc2x7Cs/Ci 
As a result, a fully differential output VOUTdiff is computed by the following equation.
VOUTdiff=(VOUT+)xe2x88x92(VOUTxe2x88x92)={(VIN+)xe2x88x92(VINxe2x88x92)}xc2x7Cs/Ci 
Namely, the fully differential output VOUTdiff is obtained by sampling a fully differential input signal (VIN+)xe2x88x92(VINxe2x88x92) and integrating the signal by using an integral gain of Cs/Ci. Besides, the inverted signal VINxe2x88x92 obtained by inverting the input signal VIN+ is expressed by VINxe2x88x92=xe2x88x92VIN+=xe2x88x92VIN. Thus, the fully differential output VOUTdiff is expressed by the following equation.
VOUTdiff=2xc2x7VINxc2x7(Cs/Ci) 
Therefore, the fully differential output VOUTdiff is obtained by sampling a single end input signal VIN at every cycle of the operating clock CK and integrating the signal by integral gain of 2xc2x7(Cs/Ci).
The above description discussed the operation of the configuration for producing a fully differential signal in a typical continuous-time system and supplying the signal to the fully differential switched capacitor circuit. Here, it should be noted that a sufficiently advanced inverter amplifier needs to be added.
Namely, it is necessary to have driving force enough to sufficiently absorb feed through noise, which is caused by turning on/off the sampling switch connected to the input terminal of the fully differential circuit on a subsequent stage, and flicker noise and thermal noise need to be sufficiently low. This is because noise occurring thus has no correlation with a positive signal, so that the noise cannot be canceled by the fully differential circuit and is added to an original signal, resulting in deterioration in S/N ratio (signal-to-noise ratio). In order to avoid the above problem, an operational amplifier which is large in area and consumed current has been used.
Further, two resistors need to be minimized in size because they cause thermal noise. However, it is necessary to improve the driving capability of the operational amplifier to drive small resistors, thereby further increasing consumed current. Moreover, when both resistance ratios cannot be obtained accurately, a gain error of an inverted signal appears. Thus, sufficient attention should be given to a layout and a manufacturing process. A method for omitting the inverter amplifier has been demanded in view of reduction in cost and consumed current and improvement in analog capability.
Considering the above circumstances, a method for producing no inverted signal in a continuous-time system and eliminating an additional inverter amplifier, that is, a so-called differential sampling method for a single end input signal has been devised. As a specific example, the following will discuss the configuration and operation of an integrator shown in FIG. 9.
In the integrator of FIG. 9, when an operating clock CK is in opposite phase (xcfx86=L, xcfx86B=H), a switch 33xe2x80x2 for discharging the lower layer electrode 27a of the first sampling capacitor 27 is connected to the input terminal 9, and a switch 43xe2x80x2 for discharging the lower layer electrode 28a of the second sampling capacitor 28 is connected to the input terminal 3. A single end input signal is supplied as a positive signal as it is from the input terminal 3. The input terminal 9 is connected to an analog ground, which is an operating reference potential of the input signal. Other configurations are the same as those of the typical fully differential circuit shown in FIG. 7.
Next, the operation of the integrator will be discussed.
When the operating clock CK is in positive phase (xcfx86=H, xcfx86B=L), the switches 31, 32, 41, and 42 are turned on and the switches 33xe2x80x2, 34, 43xe2x80x2, and 44 are turned off. Therefore, the lower layer electrode 27a of the first sampling capacitor 27 is connected to the input terminal 3, and the upper layer electrode 27b is connected to the operating common potential. Further, the lower layer electrode 28a of the second sampling capacitor 28 is connected to the input terminal 9, and the upper layer electrode 28b is connected to the operating common potential.
As a result, a positive signal potential VIN+ is inputted to the input terminal 3, and the input terminal 9 is connected to the analog ground. Thus, the following charges Q1 and Q2 are respectively accumulated in the lower layer electrodes 27a and 28a of the first and second sampling capacitors 27 and 28.
Q1=(VIN+)xc2x7Cs 
Q2=0 
Moreover, the following charges Q1xe2x80x2 and Q2xe2x80x2 are respectively accumulated in the upper layer electrodes 27b and 28b of the sampling capacitors 27 and 28.
Q1xe2x80x2=xe2x88x92(VIN+)xc2x7Cs 
Q2xe2x80x2=0 
Namely, the first sampling capacitor 27 samples an input signal, and the second sampling capacitor 28 enters a discharging state.
In contrast, when the operating clock CK is in opposite phase (xcfx86=L, xcfx86B=H), the switches 31, 32, 41, and 42 are turned off, and the switches 33xe2x80x2, 34, 43xe2x80x2, and 44 are turned on. Thus, the lower layer electrode 27a of the first sampling capacitor 27 is connected to the analog ground via the switch 33xe2x80x2, and the upper layer electrode 27b is connected to the input terminal 21. Further, the lower layer electrode 28a of the second sampling capacitor 28 is connected to the input terminal 3 via the switch 43xe2x80x2, and the upper layer electrode 28b is connected to the input terminal 22.
Therefore, charge Q1xe2x80x2 accumulated in the first sampling capacitor 27 is released and shifted to the first integral capacitor 25. Charge of xe2x88x92Q1xe2x80x2=(VIN+)xc2x7Cs is collected in the output terminal electrode of the first integral capacitor 25, and the positive output terminal 11 has a potential VOUT+ as expressed in the following equation.
VOUT+=xe2x88x92Q1xe2x80x2/Ci=(VIN+)xc2x7(Cs/Ci) 
Meanwhile, in the second sampling capacitor 28, which is discharged when the operating clock is in positive phase, the lower layer electrode 28a is connected to the input terminal 3 and has a potential of VIN+. Hence, charge of Q2xe2x80x2=xe2x88x92(VIN+)xc2x7Cs is supplied to the upper layer electrode 28b from the second integral capacitor 26. As a result, charge of xe2x88x92Q2xe2x80x2 is collected in the electrode on the input terminal 22 of the second integral capacitor 26, charge of Q2xe2x80x2=xe2x88x92(VIN+)xc2x7Cs is collected in the electrode on the output terminal, and the negative output terminal 12 has a potential VOUTxe2x88x92 as expressed by the following equation.
VOUTxe2x88x92=Q2xe2x80x2/Ci=xe2x88x92(VIN+)xc2x7(Cs/Ci) 
As a result, a fully differential output VOUTdiff is expressed by the following equation.
VOUTdiff=(VOUT+)xe2x88x92(VOUTxe2x88x92)=2xc2x7(VIN+)xc2x7(Cs/Ci) 
According to the above equation, without an additional inverter amplifier, the same result can be obtained as the fully differential circuit of FIGS. 6 and 7 for producing an inverted signal in a continuous-time system.
As described above, the differential sampling method for single end input of FIG. 9 does not require an inverter amplifier for producing an inverted signal, so that the method is excellent in cost, consumed current, noise, and so on. However, another problem has occurred because a semiconductor process has been finer recently.
Namely, regarding an input signal having a frequency of xcfx89, second harmonic distortion having a frequency of 2xcfx89 has been frequently observed. The larger voltage dependence of the following capacitor, the more adverse effect has been observed. The following will briefly discuss the cause of the effect.
As described above by using FIG. 8 a representative example of the capacitor formed on a semiconductor substrate is composed of two upper and lower polysilicon films serving as electrodes and an interlayer film composed of an oxide film and the like between the films. The finer the process, a capacitor structure has been developed with a larger capacitance per unit area. In order to increase a capacitance per area, the two upper and lower polysilicon films need to be closer to each other, namely, the oxide film serving as an interlayer film needs to be smaller in thickness.
Meanwhile, polysilicon and the like is not completely metallic and is used as a conductor by containing N-type or P-type impurity. When voltage is applied to the upper and lower polysilicon electrodes, a depletion layer is developed in a voltage direction on an interface of the bottom of the upper layer polysilicon electrode and the oxide film serving as an interlayer film or on an interface of the upper surface of the lower layer polysilicon electrode and the oxide film serving as an interlayer film. An electrically determined interlayer thickness varies according to an applied voltage.
Since the depletion layer is sufficiently small in thickness in ordinary cases, when the interlayer film has a large thickness as in the conventional process, the influence is small. In the recent fine process, as the interlayer film is smaller in thickness to several hundreds xc3x85, the influence has become larger. The influence is expressed by a change in capacitance when voltage is applied to the capacitor, that is, voltage dependence of a capacitance of the capacitor.
As a specific example, FIG. 10 shows that the first polysilicon electrode serving as a lower layer has a reference potential and the second polysilicon electrode serving as an upper layer is changed in potential. The horizontal axis indicates a potential applied to the second polysilicon electrode relative to the first polysilicon electrode. The vertical axis indicates a capacitance C(Vc) between the electrodes when voltage is applied, in a ratio relative to a reference capacitance C0 with no voltage being applied (Vc=0V).
As a specific example, FIG. 10 shows that a capacitance decreases while drawing a gentle curve according to an increase in applied voltage. Such a graph may have a rising curve due to characteristics of the manufacturing process. In formula where voltage dependence has a primary coefficient xcex1 and a secondary coefficient xcex2, a capacitance is expressed by the following equation.
C(Vc)=C0(1+xcex1Vc+xcex2Vc2+ . . . ) 
In the case of xcex1 greater than 0, a rising curve appears. In the case of xcex1 less than 0, a falling curve appears.
As described above, in the recent fine process, a primary coefficient xcex1 is extremely larger than that of the conventional process and is about several tens to several hundreds times a secondary coefficient xcex2, so that a primary coefficient xcex1 is a dominant factor. Therefore, hereinafter, an approximate expression up to a linear term is used to simplify explanation. This approximation is sufficiently proper in view of practical use.
First, in the conventional fully differential circuit using an inverter amplifier that is shown in FIGS. 6 and 7, by a one-cycle operation performed in a positive phase and a negative phase of the operating clock CK, charge quantities Q1 and Q2, which are sampled by the first and second sampling capacitors 27 and 28 and transferred to the integral capacitors 25 and 26, are expressed by the following equations.
Q1=(VIN+)xc2x7Cs=(VIN+)xc2x7Cs0(1+xcex1Vc) 
Q2=(VINxe2x88x92)xc2x7Cs=(VINxe2x88x92)xc2x7Cs0(1+xcex1Vc) 
Here, a Vc value of the first polysilicon electrode on the input side is used as a reference value. Thus, charge quantities Q1 and Q2 are expressed by the following equations.
Q1=(VIN+)xc2x7Cs0(1+xcex1(xe2x88x92VIN+)) 
Q2=(VINxe2x88x92)xc2x7Cs0(1+xcex1(xe2x88x92VINxe2x88x92)) 
Here, since VINxe2x88x92=xe2x88x92VIN+ is established, a charge quantity Q2 is expressed by the following equation.
Q2=xe2x88x92(VIN+)xc2x7Cs0(1+xcex1(VIN+)) 
Therefore, a quantity of transferred charge that contributes as a fully differential signal is expressed by the following equation.
Q1xe2x88x92Q2=(VIN+)xc2x7Cs0(1+xcex1(xe2x88x92VIN+)+1+xcex1(VIN+))=2xc2x7(VIN+)xc2x7Cs0 
As a result, the primary coefficient xcex1 of voltage dependence is completely deleted.
However, in the differential sampling method of FIG. 9, a charge quantity transferred at one cycle of the operating clock is similarly expressed by the following equation as for the first sampling capacitor 27.                     Q1        =                                            (                              VIN                +                            )                        ·            Cs                    =                                    (                              VIN                +                            )                        ·                                          Cs                0                            ⁡                              (                                  1                  +                                      α                    ⁢                                          xe2x80x83                                        ⁢                    Vc                                                  )                                                                            =                              (                          VIN              +                        )                    ·                                    CS              0                        ⁡                          (                              1                +                                  α                  ⁡                                      (                                          -                                              VIN                        +                                                              )                                                              )                                          
Meanwhile, a quantity of charge transferred from the second sampling capacitor 28 is expressed by the following equation.                     Q2        =                                            -                              (                                  VIN                  +                                )                                      ·            Cs                    =                                    -                              (                                  VIN                  +                                )                                      ·                                          Cs                0                            ⁡                              (                                  1                  +                                      α                    ⁢                                          xe2x80x83                                        ⁢                    Vc                                                  )                                                                            =                              -                          (                              VIN                +                            )                                ·                                    Cs              0                        ⁡                          (                              1                +                                  α                  ⁡                                      (                                          -                                              VIN                        +                                                              )                                                              )                                          
Therefore, a quantity of transferred charge that contributes as a fully differential signal is determined by the following equation.                               Q1          -          Q2                =                              (                          VIN              +                        )                    ·                                    Cs              0                        ⁡                          (                              1                -                                  α                  ⁡                                      (                                          VIN                      +                                        )                                                  +                1                -                                  α                  (                                      xe2x80x83                                    ⁢                                      VIN                    +                                    )                                            )                                                              =                              (                          VIN              +                        )                    ·                                    Cs              0                        ⁡                          (                              2                -                                  2                  ⁢                                      α                    ⁡                                          (                                              VIN                        +                                            )                                                                                  )                                                              =                              2            ·                          (                              VIN                +                            )                        ·                          Cs              0                                -                      2            ⁢                                                            α                  ⁡                                      (                                          VIN                      +                                        )                                                  2                            ·                              Cs                0                                                        
Therefore, a term of a voltage dependence primary coefficient xcex1 remains as a second term, which serves as a sampling error component. when a sinusoidal wave having amplitude of A at a frequency xcfx89 is considered as an input signal, VIN+=Asin(xcfx89t) is established. The above second term is expressed by the following equation.                               2          ⁢                                                    α                ⁡                                  (                                      VIN                    +                                    )                                            2                        ·                          Cs              0                                      =                  2          ⁢                      α            ·                          A              2                        ·                                          sin                2                            ⁡                              (                                  ω                  ⁢                                      xe2x80x83                                    ⁢                  t                                )                                      ·                          Cs              0                                                              =                  α          ·                      Cs            0                    ·                                    A              2                        ⁡                          (                              1                -                                  cos                  ⁡                                      (                                          2                      ⁢                      ω                      ⁢                                              xe2x80x83                                            ⁢                      t                                        )                                                              )                                          
Since the above equation includes cos(2xcfx89t), a frequency component twice an input signal, that is, a second harmonic distortion component is generated. When the second harmonic distortion component is normalized by an original sampling charge quantity with respect to an input signal, xcex1A/2 is obtained. When xcex1 is at 100 ppm/V or less at A=1 V, the second harmonic distortion is about xe2x88x9286 dB.
However, in the recent fine process of semiconductor integrated circuits, xcex1 is increased from several hundreds ppm/V to about 1000 ppm/V in many cases. In the case of 1000 ppm/V, the second harmonic distortion increases to about xe2x88x9266 dB.
Regarding kinds of analog ICs such as an A/D converter used for audio, a permissible level of a harmonic distortion component with respect to an input signal has been generally xe2x88x9280 dB or less at the minimum in recent years, so that the above harmonic distortion of about xe2x88x9266 dB is at an analog characteristic level unsuitable for use.
Hence, the first object of the present invention is to provide a fully differential sampling circuit which reduces a sampling error so as to suppress the occurrence of a second harmonic component. The sampling error results from voltage dependence of a capacitance of a capacitor formed on a semiconductor substrate.
The second object of the present invention is to provide a delta sigma modulator, an A/D converter, and a switched capacitor filter circuit that can reduce cost and increase accuracy by including the above-mentioned fully differential sampling circuit.
The present invention comprises first and second sampling capacitors each composed of two upper and lower layer electrodes formed on a semiconductor substrate and a dielectric film between the electrodes, a first switch group for charging and discharging the first sampling capacitor, a second switch group for charging and discharging the second sampling capacitor, and a fully differential operational amplifier which connects a first integral capacitor between a negative input terminal and a positive output terminal and connects a second integral capacitor between a positive input terminal and a negative output terminal. The first switch group connects the first sampling capacitor between the first input terminal and a ground in a first period and between the second input terminal and the negative input terminal of the fully differential operational amplifier in a second period, and the second switch group connects the second sampling capacitor between the second input terminal and the ground in the first period and between the first input terminal and the positive input terminal of the fully differential operational amplifier in the second period. Further, the first sampling capacitor and the second sampling capacitor are opposite to each other in connecting direction.
Moreover, the present invention comprises first and second sampling capacitors each composed of two upper and lower layer electrodes formed on a semiconductor substrate and a dielectric film between the electrodes, first to fourth switches for charging and discharging the first sampling capacitor, fifth to eighth switches for charging and discharging the second sampling capacitor, and a fully differential operational amplifier which connects a first integral capacitor between a negative input terminal and a positive output terminal and connects a second integral capacitor between a positive input terminal and a negative output terminal. One of electrodes of the first sampling capacitor is connected to a first input terminal via the first switch and is connected to a second input terminal via the third switch, and the other electrode of the first sampling capacitor is grounded via the second switch and is connected to one of input terminals of the fully differential operational amplifier via the fourth switch. Moreover, one of electrodes of the second sampling capacitor is connected to the second input terminal via the fifth switch and is connected to a first input terminal via the seventh switch, and the other electrode of the second sampling capacitor is grounded via the sixth switch and is connected to the other input terminal of the fully differential operational amplifier via the eighth switch. Further, the first sampling capacitor and the second sampling capacitor are opposite to each other in connecting direction.
Besides, according to the present invention, in the fully differential sampling circuit, the first and second integral capacitors are each composed of the two upper and lower layer electrodes formed on the semiconductor substrate and the dielectric film between the electrodes. The first integral capacitor and the second integral capacitor have the same electrodes respectively connected to the corresponding input terminals of the fully differential operational amplifier.
Namely, when the upper layer electrode of the first integral capacitor is connected to the negative input terminal of the differential operational amplifier, the upper layer electrode of the second integral capacitor is also connected to the positive input terminal of the differential operational amplifier. When the lower layer electrode of the first integral capacitor is connected to the negative input terminal of the differential operational amplifier, the lower layer electrode of the second integral capacitor is also connected to the positive input terminal of the differential operational amplifier.
Additionally, according to the present invention, in the above fully differential sampling circuit, the fully differential operational amplifier includes positive and negative feedback paths, the positive and negative feedback paths include at least a first feedback capacitor and a second feedback capacitor which are each composed of two upper and lower layer electrodes formed on the semiconductor substrate and the dielectric film between the electrodes, and the first feedback capacitor and the second feedback capacitor are connected in the same direction.
Namely, when the upper layer electrode of the first feedback capacitor is connected to the negative input terminal of the fully differential operational amplifier, the upper layer electrode of the second feedback capacitor is also connected to the positive input terminal of the fully differential operational amplifier. When the lower layer electrode of the first feedback capacitor is connected to the negative input terminal of the fully differential operational amplifier, the lower layer electrode of the second feedback capacitor is also connected to the positive input terminal of the fully differential operational amplifier.
As described above, according to the present invention, the first and second sampling capacitors are each composed of the two upper and lower layer electrodes formed on the semiconductor substrate and the dielectric film between the electrodes, and the capacitors are opposite to each other in connecting direction.
Hence, according to the present invention, it is possible to eliminate conventional second harmonic distortion appearing depending upon a voltage coefficient of a capacitance of the capacitor formed on the semiconductor substrate, thereby achieving high performance.
Further, according to the present invention, even when the inverter amplifier is unnecessary, fully differential sampling can be performed from a single end input signal. Thus, the manufacturing cost can be reduced by omitting the inverter amplifier.
In order to attain the second object of the present invention, the following configuration is devised.
In a delta sigma modulator, the above fully differential sampling circuit is used as the sampling/holding function of the delta sigma modulator and the integrating function of a first stage.
The fully differential delta sigma modulator and a digital decimation filter constitute an A/D converter.
Moreover, in a switched capacitor filter circuit, a fully differential sampling circuit is disposed as a circuit of the first stage.
As described above, since the present invention includes the fully differential sampling circuit, it is possible to reduce the cost and increase accuracy.